Field of the Invention
The invention relates to a field-effect transistor structure in which the gate electrode is separated by an insulation layer from an inversion channel in the semiconductor layer lying underneath. The invention relates, in particular, to a silicon-based field-effect transistor of this type, wherein a SiO2 layer is used as the insulation layer.
A field-effect transistor is a semiconductor component with three terminals which are referred to as the gate, source and drain. In a field-effect transistor, the conductivity of the drain-source path is influenced with a control voltage applied to the gate, during which process no control current flows so that the control is carried out without any consumption of power. By means of the control voltage applied to the gate which is insulated from the drain-source path by means of an insulation layer, the charge carrier density is determined in the inversion layer which is located underneath the gate and forms a conductive channel between the drain and the source, thus permitting current flow. Without such an inversion layer, at least one of the pn-type junctions between the source and the semiconductor substrate or the drain and the semiconductor substrate is always switched off so that no current flows in the field-effect transistor. Depending on the doping of the channel in the semiconductor substrate between the drain and the source, the field-effect transistor is normally on or normally off. In the case of normally on field-effect transistors, a drain current flows without a voltage being applied between the drain and the source, whereas it does not flow in normally off field-effect transistors.
Such field-effect transistors with an insulated gate, also referred to in the following as MISFET or as a MOSFET if an oxide is used as the insulation layer, are used in particular as an active component in highly integrated silicon-based circuits because field-effect transistors can be fabricated very easily and in a very space-saving way. Here, in particular, field-effect transistors in which the insulation layer is composed of SiO2 and the gate electrode of polysilicon have become customary. Polysilicon can be deposited at relatively low temperatures and also be made highly conductive by doping. Furthermore, a polysilicon can be precisely structured using a dry etching process.
The insulation layers between the gate and the inversion channel in the semiconductor substrate are being made increasingly thin by means of the increasing miniaturization of the MISFET structures in integrated circuits. In the known MISFET structures, there is then however an amplified tunnel current which is caused by the fact that charge carriers of the inversion layer, which is formed underneath the gate electrode by the control voltage applied via the gate, penetrate the potential wall formed by the insulation layer. The tunnel current depends exponentially on the thickness of the insulation layer between the gate and the channel. No MISFET structures have been known hitherto in the prior art in which this undesired tunnel current can be suppressed.
The object of the present invention is to provide a field-effect transistor with an insulated gate which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this general kind, and in which a tunnel current composed of charge carriers from the inversion layer under the gate electrode through the insulation layer is significantly reduced.
With the above and other objects in view there is provided, in accordance with the invention, a field-effect transistor, comprising:
a source electrode and a drain electrode formed in a semiconductor substrate;
an inversion channel formed in the semiconductor substrate between the source electrode and the drain electrode, the inversion channel having a given energy interval for controlling a charge carrier density in the inversion channel;
a gate electrode disposed between the source electrode and the drain electrode and fabricated from a material having no energetically permitted state in a range of the given energy interval; and
an insulation layer separating the gate electrode from the inversion channel.
In other words, the gate electrode which is separated from a channel between a source electrode and a drain electrode in a semiconductor substrate by an insulation layer is composed of a material which does not have any permitted states in an energy interval which is used to control the charge carrier density in the inversion channel.
By means of this configuration of the field-effect transistor, direct tunneling of the charge carriers from the source-drain channel into the gate electrode is significantly suppressed because the charge carriers which tunnel from the semiconductor substrate through the insulation layer do not find any permitted states in the gate electrode. Direct tunneling from the inversion channel in the semiconductor substrate into the gate electrode is thus not possible. For this reason, charge carriers can find free states in the gate electrode only by involving phonons which are excited in the gate electrode. The probability of such phonon-assisted tunneling is, however, very low so that this results in only a negligible tunnel current, even with very thin insulation layers. According to the invention, the field-effect transistor is therefore controlled virtually without the consumption of power even with a very thin insulation layer. This is advantageous in particular if the highly integrated circuits which are equipped with such field-effect transistors are operated with battery support, for example in laptops.
In accordance with an added feature of the invention, the gate electrode is formed from a material with a crystalline structure, and the material has a band gap in the given energy interval that is used to control the charge carrier density in the inversion channel between the source and the gate.
In accordance with an additional feature of the invention, the band gap of the gate electrode comprises an energy level of a basic state of the charge carriers in the inversion channel between the source electrode and the drain electrode.
In accordance with another feature of the invention, the gate electrode is formed of a material having a band gap in an electronic band structure in an energy range of up to 2 eV above the Fermi level.
According to this preferred embodiment, the gate electrode is composed of a material with a crystalline structure which has a band gap in the band structure in the energy interval in the range up to 2 eV above the Fermi level. This configuration of the gate electrode makes it possible to reliably prevent elastic tunneling of charge carriers through the insulation layer in the energy range which comprises the voltage differential which is used to control the charge carrier density and is usually applied between the gate electrode and the source electrode.
In accordance with a concomitant feature of the invention, the semiconductor substrate is a silicon semiconductor substrate, and the gate electrode is formed of 2H-TaS2.
In this preferred embodiment, an n-type channel is formed in a silicon layer between the source electrode and the drain electrode, 2H-TaS2 being used as the material for the gate electrode. This configuration makes it possible largely to suppress direct tunneling in standard silicon-based MISFETs so that the semiconductor structure according to the invention can be fabricated with the known silicon planar technology.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a field-effect transistor structure with an insulated gate, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.